From 521e48c87da6c70644a03c7b5e77856a8e556e53 Mon Sep 17 00:00:00 2001 From: praveen hodagatta pranesh Date: Thu, 27 Sep 2018 00:00:13 +0800 Subject: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions - CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/romstage/fsp_params.c') diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6b3ccb2a0d..3cfa2819c2 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -31,7 +31,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->SaGv = config->SaGv; - if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H)) + if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)) m_cfg->UserBd = BOARD_TYPE_DESKTOP; else m_cfg->UserBd = BOARD_TYPE_ULT_ULX; -- cgit v1.2.3