From 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 20 Feb 2019 16:39:55 -0700 Subject: soc/intel/cannonlake: Set correct serirq mode Set FSP params PchSirqEnable/PchSirqMode based on board setting of serirq_mode. Matches implementation on Skylake. This is a no-change for existing boards since the default remains SERIRQ_QUIET mode. Tested on system76 galp3-c, out-of-tree WHL-U board Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Signed-off-by: Jeremy Soller Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Nathaniel L Desimone --- src/soc/intel/cannonlake/lpc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/cannonlake/lpc.c') diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c4eb884a75..8b9802220e 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -210,6 +210,8 @@ static void pch_misc_init(void) void lpc_soc_init(struct device *dev) { + const config_t *config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); pch_misc_init(); @@ -218,10 +220,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (CONFIG(SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); + lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ pch_enable_ioapic(dev); -- cgit v1.2.3