From dce635977381ff293f7f74c5cdfae142f36412d8 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 17 Sep 2019 18:48:00 +0200 Subject: soc/intel/cannonlake: lockdown: lock global reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/lockdown.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/cannonlake/lockdown.c') diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index ba68aa385c..c556839d18 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -60,6 +61,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); -- cgit v1.2.3