From 6cf501c3ae0278092cb76ccab015ad891af1fd48 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 10 Oct 2017 18:26:18 -0700 Subject: soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/lockdown.c | 113 ++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 src/soc/intel/cannonlake/lockdown.c (limited to 'src/soc/intel/cannonlake/lockdown.c') diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c new file mode 100644 index 0000000000..dba59014db --- /dev/null +++ b/src/soc/intel/cannonlake/lockdown.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) + +static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +{ + uint8_t *pmcbase; + uint32_t reg32, pmsyncreg; + + /* PMSYNC */ + pmcbase = pmc_mmio_regs(); + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PMSYNC_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + + /* Lock down ABASE and sleep stretching policy */ + reg32 = read32(pmcbase + GEN_PMCON_B); + reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + write32(pmcbase + GEN_PMCON_B, reg32); + + if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + pmcbase = pmc_mmio_regs(); + reg8 = read8(pmcbase + GEN_PMCON_B); + reg8 |= SMI_LOCK; + write8(pmcbase + GEN_PMCON_B, reg8); + } +} + +static void dmi_lockdown_cfg(void) +{ + /* + * GCS reg of DMI + * + * When set, prevents GCS.BBS from being changed + * GCS.BBS: (Boot BIOS Strap) This field determines the destination + * of accesses to the BIOS memory range. + * Bits Description + * “0b”: SPI + * “1b”: LPC/eSPI + */ + pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); +} + +static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config) +{ + /* Set FAST_SPI opcode menu */ + fast_spi_set_opcode_menu(); + + /* Discrete Lock Flash PR registers */ + fast_spi_pr_dlock(); + + /* Lock FAST_SPIBAR */ + fast_spi_lock_bar(); + + /* Set Bios Interface Lock, Bios Lock */ + if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* Bios Interface Lock */ + fast_spi_set_bios_interface_lock_down(); + + /* Bios Lock */ + fast_spi_set_lock_enable(); + } +} + +static void platform_lockdown_config(void *unused) +{ + struct soc_intel_cannonlake_config *config; + struct device *dev; + + dev = PCH_DEV_SPI; + /* Check if device is valid, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* SPI lock down configuration */ + spi_lockdown_cfg(config); + + /* DMI lock down configuration */ + dmi_lockdown_cfg(); + + /* PMC lock down configuration */ + pmc_lockdown_cfg(config); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, + NULL); -- cgit v1.2.3