From c004857da06dd90be9a1ac34bd6efe2bc03fed6a Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Wed, 15 Jan 2020 11:17:21 +0800 Subject: soc/intel/cannonlake: Add chip config for SATA strength Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/sata.h | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/soc/intel/cannonlake/include/soc/sata.h (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/sata.h b/src/soc/intel/cannonlake/include/soc/sata.h new file mode 100644 index 0000000000..17802c3412 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/sata.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_SATA_H_ +#define _SOC_SATA_H_ + +#include + +/* SATA Gen3 strength */ +struct sata_port_config { + uint8_t RxGen3EqBoostMagEnable; + uint8_t RxGen3EqBoostMag; + uint8_t TxGen3DownscaleAmpEnable; + uint8_t TxGen3DownscaleAmp; + uint8_t TxGen3DeEmphEnable; + uint8_t TxGen3DeEmph; +}; + +#endif -- cgit v1.2.3