From ae1548621acae99b7f7ac4a722607af0a4a0c825 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Tue, 1 Aug 2017 11:32:06 -0700 Subject: soc/cannonlake: Enable SMM code for Cannon Lake The minimum needed defines are included here and pm.h will be updated when the PMC code for cannonlake is uploaded. Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776 Signed-off-by: Brandon Breitenstein Reviewed-on: https://review.coreboot.org/20849 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/pm.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index d69250776c..66541228fe 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -20,6 +20,23 @@ #include #include +#define PM1_EN 0x02 +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define SMI_EN 0x30 +#define ESPI_SMI_EN (1 << 28) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) + + +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define PME_B0_EN (1 << 13) + +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; -- cgit v1.2.3