From 73b1bd7992fb33f33c33747fd0919fc495c3d5c4 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 28 Nov 2019 13:56:24 +0530 Subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/include/soc/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index e7056ebcec..efed88180c 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -28,6 +28,12 @@ #ifndef __ACPI__ struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); +/* + * Routine to perform below operations: + * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 2. Program GPIO PM configuration based on PM mask and value + */ +void soc_gpio_pm_configuration(void); #endif #endif -- cgit v1.2.3