From 70de396958627680a16992fbb8c5e6652dd35bf4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 21 Jul 2017 17:09:41 +0000 Subject: Revert "soc/intel/cannonlake: Call into FSP siliconinit" This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/ramstage.h | 28 ------------------------- 1 file changed, 28 deletions(-) delete mode 100644 src/soc/intel/cannonlake/include/soc/ramstage.h (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h deleted file mode 100644 index 4a96185e6b..0000000000 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include -#include -#include -#include - -void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void soc_init_pre_device(void *chip_info); - -#endif -- cgit v1.2.3