From 5ff742c740c3d39df85596a99046ef88aef5351f Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 27 Dec 2018 17:01:09 -0800 Subject: soc/intel/cannonlake: Add cannonlake ACPI GPIO op Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implement GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform, add an dummy STSX in DSDT table, read back from iotools to confirm the GPIO tx state get updated. Signed-off-by: Lijian Zhao Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Reviewed-on: https://review.coreboot.org/c/30461 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/include/soc/gpio_defs.h | 1 + src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 1 + 2 files changed, 2 insertions(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 716f59d1c1..c282000d7e 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -252,4 +252,5 @@ #define GPIORXSTATE_MASK 0x1 #define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index ab04142551..d8d002cad0 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -326,4 +326,5 @@ #define GPIORXSTATE_MASK 0x1 #define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 #endif -- cgit v1.2.3