From 408d76f8673ec69ae8b48ad93e0889d46652c322 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Fri, 1 Dec 2017 12:53:43 -0800 Subject: soc/intel/cannonlake: Add support for D0 stepping D0 stepping with CPUID 0x60663 need to be added in coreboot. TEST=Boot up with D0 stepping processor Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/22676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/include/soc/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index bd9db37848..e50801f0b0 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -25,6 +25,7 @@ #define CPUID_CANNONLAKE_A0 0x60660 #define CPUID_CANNONLAKE_B0 0x60661 #define CPUID_CANNONLAKE_C0 0x60662 +#define CPUID_CANNONLAKE_D0 0x60663 /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e -- cgit v1.2.3