From 2de19038beffa154eefe40755b607aa9f94d9f9f Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Thu, 14 Mar 2019 23:23:22 +0530 Subject: soc/intel/cannonlake: Clear PMCON status bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. BUG=b:128482282 BRANCH=None TEST=In cbmem logs, check for value of “prev_sleep_state” using command cbmem –c | grep “prev_sleep_state” For cold reboot, "prev_sleep_state 5" For warm reboot, "prev_sleep_state 0" Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi --- src/soc/intel/cannonlake/include/soc/pm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index c8df25a024..5b85e74bf5 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -169,5 +169,8 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); +/* Clear PMCON status bits */ +void pmc_clear_pmcon_sts(void); + #endif /* !defined(__ACPI__) */ #endif -- cgit v1.2.3