From 03e44f46b080022a0c8949b2cc7ba88d587e671e Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Tue, 25 Jul 2017 18:42:29 -0700
Subject: soc/intel/cannonlake: Correct gpio definition

The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.

Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/soc/intel/cannonlake/include/soc/gpio_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/soc/intel/cannonlake/include')

diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 46ab1d98c6..6e84f838f1 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -22,7 +22,7 @@
 #include <soc/gpio_soc_defs.h>
 
 
-#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
 
 #define NUM_GPIO_COMx_GPI_REGS(n)	\
 		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
-- 
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