From 009e6cbf842ae1e28231d8e864403c68857c337a Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 13 Mar 2019 10:52:49 -0700 Subject: soc/intel/cannonlake: Ignore GBE LTR Ignore integrated GBE controller LTR setting to make it wake up from s0ix with 10/100M cable attached. BUG=b:122435844 TEST= Test on sarien platorm, after the changes sytem can wake by WOL, and also checked SLP_S0 residency can increase with 10/100M cable and battery connected. Signed-off-by: Lijian Zhao Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/cannonlake/include/soc/pmc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/cannonlake/include') diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 95cca65ab2..67854d4cbd 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -145,6 +145,9 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define LTR_IGN 0x1B0C +#define IGN_GBE (1 << 3) + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) -- cgit v1.2.3