From ad87d1c8b9285cfed47b3ec060be520a467189ff Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:04:57 +0200 Subject: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/cannonlake/graphics.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/cannonlake/graphics.c') diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index c2f99570b7..1ecbb67098 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -48,9 +48,8 @@ void graphics_soc_init(struct device *dev) } /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); /* * GFX PEIM module inside FSP binary is taking care of graphics -- cgit v1.2.3