From 76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 May 2019 21:23:18 +0530 Subject: soc/intel/cannonlake: Make use of gpio_pm_configure() Provide option in chip.h to set dynamic local clock gating setting. BUG=b:130764684 TEST=Able to build and boot CML. Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/gpio.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/cannonlake/gpio.c') diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index dd514643d7..4036fdc073 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -77,8 +77,9 @@ static const struct pad_group cnl_community4_groups[] = { INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ }; -static const struct pad_community cnl_communities[] = { - { /* GPP A, B, G, SPI */ +static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = { + /* GPP A, B, G, SPI */ + [COMM_0] = { .port = PID_GPIOCOM0, .first_pad = GPP_A0, .last_pad = GPIO_RSVD_11, @@ -96,7 +97,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, .num_groups = ARRAY_SIZE(cnl_community0_groups), - }, { /* GPP D, F, H, VGPIO */ + }, + /* GPP D, F, H, VGPIO */ + [COMM_1] = { .port = PID_GPIOCOM1, .first_pad = GPP_D0, .last_pad = vSD3_CD_B, @@ -114,7 +117,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, .num_groups = ARRAY_SIZE(cnl_community1_groups), - }, { /* GPD */ + }, + /* GPD */ + [COMM_2] = { .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -132,7 +137,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, .num_groups = ARRAY_SIZE(cnl_community2_groups), - }, { /* AZA, CPU */ + }, + /* AZA, CPU */ + [COMM_3] = { .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, .last_pad = GPIO_RSVD_38, @@ -150,7 +157,9 @@ static const struct pad_community cnl_communities[] = { .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, .num_groups = ARRAY_SIZE(cnl_community3_groups), - }, { /* GPP C, E, JTAG, HVMOS */ + }, + /* GPP C, E, JTAG, HVMOS */ + [COMM_4] = { .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPIO_RSVD_27, -- cgit v1.2.3