From 9bf1d8f2761d3f83123222225aab2673cde466a7 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 13 Dec 2018 09:12:34 -0800 Subject: soc/intel/cannonlake: SATA and DMI power optimize Expose the FSP interface to enable SATA and PCH side DMI power optimize options. Actual step executed in FSP, step defined in cannonlake pch BIOS spec(CDI# 570374). Signed-off-by: Lijian Zhao Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 Reviewed-on: https://review.coreboot.org/c/30211 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/cannonlake/fsp_params.c') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a9326a41bf..78b27e9514 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -221,6 +221,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; + + /* Power Optimizer */ + params->PchPwrOptEnable = config->dmipwroptimize; + params->SataPwrOptEnable = config->satapwroptimize; } /* Mainboard GPIO Configuration */ -- cgit v1.2.3