From 009e6cbf842ae1e28231d8e864403c68857c337a Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 13 Mar 2019 10:52:49 -0700 Subject: soc/intel/cannonlake: Ignore GBE LTR Ignore integrated GBE controller LTR setting to make it wake up from s0ix with 10/100M cable attached. BUG=b:122435844 TEST= Test on sarien platorm, after the changes sytem can wake by WOL, and also checked SLP_S0 residency can increase with 10/100M cable and battery connected. Signed-off-by: Lijian Zhao Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/cannonlake/fsp_params.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/cannonlake/fsp_params.c') diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 6173403395..25ee5e1ebe 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -107,6 +107,17 @@ static void parse_devicetree(FSP_S_CONFIG *params) parse_devicetree_param(config, params); } +/* Ignore LTR value for GBE devices */ +static void ignore_gbe_ltr(void) +{ + uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg8 = read8(pmcbase + LTR_IGN); + reg8 |= IGN_GBE; + write8(pmcbase + LTR_IGN, reg8); +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -168,6 +179,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmSlpS0VmRuntimeControl = 0; params->PchPmSlpS0Vm070VSupport = 0; params->PchPmSlpS0Vm075VSupport = 0; + ignore_gbe_ltr(); } } -- cgit v1.2.3