From 3cce7a0311b85f22e3b653bee1bf1c0e4c7e4e45 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 6 Feb 2019 15:21:55 -0800 Subject: soc/intel/cannonlake: Add field to identify single channel memory Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/cnl_memcfg_init.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/cannonlake/cnl_memcfg_init.c') diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 4425862c32..e97b5711e8 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -49,14 +49,16 @@ static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, } static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *board_cfg, + const struct cnl_mb_cfg *cnl_cfg, size_t spd_data_len, uintptr_t spd_data_ptr) { mem_cfg->MemorySpdDataLen = spd_data_len; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - /* Use the same spd data for channel 1, Dimm 0 */ - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + if (cnl_cfg->channel_empty[0] == 0) + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + + if (cnl_cfg->channel_empty[1] == 0) + mem_cfg->MemorySpdPtr10 = spd_data_ptr; } /* -- cgit v1.2.3