From c004857da06dd90be9a1ac34bd6efe2bc03fed6a Mon Sep 17 00:00:00 2001
From: Jamie Chen <jamie.chen@intel.com>
Date: Wed, 15 Jan 2020 11:17:21 +0800
Subject: soc/intel/cannonlake: Add chip config for SATA strength

Add config to chip.h for tuning SATA gen3 strength.

BUG=b:147351936
BRANCH=none
TEST=build successful in puff

Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/cannonlake/chip.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/intel/cannonlake/chip.h')

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 07a67cd630..0712146544 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -29,6 +29,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/pmc.h>
+#include <soc/sata.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>
@@ -39,6 +40,7 @@
 #endif
 
 #define SOC_INTEL_CML_UART_DEV_MAX 3
+#define SOC_INTEL_CML_SATA_DEV_MAX 8
 
 struct soc_intel_cannonlake_config {
 
@@ -390,6 +392,9 @@ struct soc_intel_cannonlake_config {
 	/* SATA Power Optimizer */
 	uint8_t satapwroptimize;
 
+	/* SATA Gen3 Strength */
+	struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX];
+
 	/* Enable or disable eDP device */
 	uint8_t DdiPortEdp;
 
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