From a979460614db63212f04658a592bd883f8e28b80 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Thu, 8 Apr 2021 20:31:47 +0530 Subject: soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/cannonlake/chip.h') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f84a48015e..3c8a68baf1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -156,10 +156,10 @@ struct soc_intel_cannonlake_config { /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Implemented as slot or built-in? */ -- cgit v1.2.3