From 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 20 Feb 2019 16:39:55 -0700
Subject: soc/intel/cannonlake: Set correct serirq mode

Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.

This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.

Tested on system76 galp3-c, out-of-tree WHL-U board

Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
---
 src/soc/intel/cannonlake/chip.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/intel/cannonlake/chip.h')

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 330555c0c0..b14c3c50dc 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -22,6 +22,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
 #include <smbios.h>
 #include <stdint.h>
 #include <soc/gpio.h>
@@ -360,6 +361,8 @@ struct soc_intel_cannonlake_config {
 	 */
 	uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
 
+	enum serirq_mode serirq_mode;
+
 	/* GPIO SD card detect pin */
 	unsigned int sdcard_cd_gpio;
 
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