From 1159a163cd36318d27f8f3b71617ad4a5b781efb Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 22 Apr 2019 10:45:51 -0700 Subject: soc/intel/cnl: Enable VT-d Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Pratikkumar V Prajapati --- src/soc/intel/cannonlake/chip.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/intel/cannonlake/chip.h') diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f34528a017..2b2a51f6a0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -344,9 +344,6 @@ struct soc_intel_cannonlake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* Intel VT configuration */ - uint8_t VtdDisable; - /* * Acoustic Noise Mitigation * 0b - Disable -- cgit v1.2.3