From 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 12 Oct 2019 15:16:33 +0200 Subject: intel/cannonlake: Implement PCIe RP devicetree update Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Patrick Rudolph Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/chip.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/soc/intel/cannonlake/chip.c') diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 51678add67..ef85215623 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,19 @@ #include "chip.h" +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -166,6 +180,12 @@ void soc_init_pre_device(void *chip_info) cnl_configure_pads(NULL, 0); soc_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + pcie_rp_update_devicetree(pch_h_rp_groups); + else + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { -- cgit v1.2.3