From 2410cd937925df60934855c885a16c40d2d69739 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 26 Mar 2018 02:25:07 -0700 Subject: soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb. Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/25366 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Lijian Zhao Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/chip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/cannonlake/chip.c') diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index b2689b0608..590bb4559d 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -180,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; FSP_S_CONFIG *params = &supd->FspsConfig; - const struct device *dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; /* Parse device tree and enable/disable devices */ @@ -262,7 +263,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } - params->XdciEnable = config->XdciEnable; + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { -- cgit v1.2.3