From a00e10474a33387a46197ee1985da7bd9b6deb6f Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 5 Jun 2017 13:22:59 -0700 Subject: soc/intel/cannonlake: Add report_platform.c Dump basic platform information early in bootblock. Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/20068 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- .../intel/cannonlake/bootblock/report_platform.c | 159 +++++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 src/soc/intel/cannonlake/bootblock/report_platform.c (limited to 'src/soc/intel/cannonlake/bootblock') diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c new file mode 100644 index 0000000000..c50814230d --- /dev/null +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIOS_SIGN_ID 0x8B + +static struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_CANNONLAKE_A0, "Cannonlake A0" }, + { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, + { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, +}; + +static struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, + { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, +}; + +static struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, +}; + +static void report_cpu_info(void) +{ + struct cpuid_result cpuidr; + u32 i, index; + char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + int vt, txt, aes; + msr_t microcode_ver; + static const char * const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + } else { + u32 p[13]; + int j=0; + + for (i = 2; i <= 4; i++) { + cpuidr = cpuid(index + i); + p[j++] = cpuidr.eax; + p[j++] = cpuidr.ebx; + p[j++] = cpuidr.ecx; + p[j++] = cpuidr.edx; + } + p[12]=0; + cpu_name = (char *)p; + } + /* Skip leading spaces in CPU name string */ + while (cpu_name[0] == ' ') + cpu_name++; + + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(BIOS_SIGN_ID, microcode_ver); + cpuidr = cpuid(1); + microcode_ver = rdmsr(BIOS_SIGN_ID); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpuidr.eax) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpuidr.eax, cpu_type, microcode_ver.hi); + + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +static void report_mch_info(void) +{ + int i; + u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, mch_revision, mch_type); +} + +static void report_igd_info(void) +{ + int i; + u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_igd_info(); +} -- cgit v1.2.3