From 39e1f44f331040b2e9574e9c792f583b8c6a5aba Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 8 Jan 2020 15:22:13 -0800 Subject: soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/bootblock/report_platform.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/cannonlake/bootblock') diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 19dce0002a..67dd452e8e 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -83,6 +83,8 @@ static struct { { PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" }, { PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" }, + { PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_4_2, "CometLake-H (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" }, -- cgit v1.2.3