From e7a1e7d3c49e980774985f3f6fae697dcb129420 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 9 Oct 2017 18:39:30 -0700 Subject: soc/intel/cannonlake: Fix HECI error on reset Move HECI init from bootblock to romstage, the HECI bar saved by CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage will be read back from PCI. Also add fail safe option to reset in case of HECI command not successful. TEST= Force global reset from FSP and read back HECI bar in debug print. Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21930 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/bootblock/pch.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/intel/cannonlake/bootblock/pch.c') diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 091e6f7cbc..0deece6521 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -194,6 +193,4 @@ void pch_early_init(void) smbus_common_init(); enable_rtc_upper_bank(); - - heci_init(HECI1_BASE_ADDRESS); } -- cgit v1.2.3