From ad87d1c8b9285cfed47b3ec060be520a467189ff Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:04:57 +0200 Subject: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/cannonlake/bootblock/pch.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/cannonlake/bootblock/pch.c') diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index d67edea21c..516359daec 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -61,22 +61,21 @@ static uint32_t get_pmc_reg_base(void) static void soc_config_pwrmbase(void) { uint32_t reg32; + uint16_t reg16; /* * Assign Resources to PWRMBASE * Clear BIT 1-2 Command Register */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MEMORY); - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); /* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); /* Enable Bus Master and MMIO Space */ - reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; - pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Enable PWRM in PMC */ reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); -- cgit v1.2.3