From 9b50a57e4343ce77b8ae1aaca5a3866599056456 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 21 Dec 2017 13:40:07 -0800 Subject: soc/intel/cannonlake: Program DMI PCR settings According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/bootblock/pch.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/soc/intel/cannonlake/bootblock/pch.c') diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 47eaceb3f9..ae413d5813 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -39,11 +39,6 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_DMI_LPCLGIR1 0x2730 -#define PCR_DMI_LPCLGIR2 0x2734 -#define PCR_DMI_LPCLGIR3 0x2738 -#define PCR_DMI_LPCLGIR4 0x273c - #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC @@ -176,7 +171,7 @@ void pch_early_iorange_init(void) } /* IO Decode Enable */ - dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN; + dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN; pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); } -- cgit v1.2.3