From 031020e431f8d013108957b856da5ff5c7c596f3 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Fri, 15 Dec 2017 12:58:07 -0800
Subject: soc/intel/cannonlake: Correct PMC/GPIO routing information

PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add
function call to set up GPE routing in bootblock stage.

TEST=Boot up into OS, and manually check PMC GPE status

Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/soc/intel/cannonlake/bootblock/pch.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/cannonlake/bootblock/pch.c')

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 0deece6521..cca70c21ad 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -18,6 +18,7 @@
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
@@ -192,5 +193,8 @@ void pch_early_init(void)
 	/* Program SMBUS_BASE_ADDRESS and Enable it */
 	smbus_common_init();
 
+	/* Set up GPE configuration */
+	pmc_gpe_init();
+
 	enable_rtc_upper_bank();
 }
-- 
cgit v1.2.3