From e58eafc45a67a25ffd19b43d9bd845290a87b71c Mon Sep 17 00:00:00 2001 From: Praveen Hodagatta Pranesh Date: Wed, 27 Nov 2019 13:47:09 +0800 Subject: soc/intel/cannonlake: Fix compilation Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/bootblock/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/cannonlake/bootblock/bootblock.c') diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f8539766c..6a6dd8be25 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ const FSPT_UPD temp_ram_init_params = { * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, -- cgit v1.2.3