From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/cannonlake/acpi/scs.asl | 4 ++-- src/soc/intel/cannonlake/acpi/southbridge.asl | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/cannonlake/acpi') diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 1806e75e87..cdfff911b8 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -112,7 +112,7 @@ Scope (\_SB.PCI0) { And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to Native */ GPMO(SD_PWR_EN_PIN, 0x1) #endif @@ -126,7 +126,7 @@ Scope (\_SB.PCI0) { Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) -#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) +#if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) /* Change pad mode to GPIO control */ GPMO(SD_PWR_EN_PIN, 0x0) diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ae8de6a1df..d9ff70b6bc 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -30,7 +30,7 @@ #include "scs.asl" /* GPIO controller */ -#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) #include "gpio_cnp_h.asl" #else #include "gpio.asl" -- cgit v1.2.3