From 521e48c87da6c70644a03c7b5e77856a8e556e53 Mon Sep 17 00:00:00 2001 From: praveen hodagatta pranesh Date: Thu, 27 Sep 2018 00:00:13 +0800 Subject: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions - CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/acpi/southbridge.asl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl') diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ff323c40a3..49b5f6e509 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -33,7 +33,11 @@ #include "scs.asl" /* GPIO controller */ +#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#include "gpio_cnp_h.asl" +#else #include "gpio.asl" +#endif /* LPC 0:1f.0 */ #include "lpc.asl" -- cgit v1.2.3