From ae565463b6a7ad4edad76ff8e2f52e1176bf8783 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 2 Oct 2017 19:18:16 -0700 Subject: soc/intel/cannonlake: Add all the SOC level DSDT tables Add all the SOC level DSDT tables, reference from skylake/kabylake. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21860 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/acpi/smbus.asl | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 src/soc/intel/cannonlake/acpi/smbus.asl (limited to 'src/soc/intel/cannonlake/acpi/smbus.asl') diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl new file mode 100644 index 0000000000..cd5ba2c822 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/smbus.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Intel SMBus Controller 0:1f.4 + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} -- cgit v1.2.3