From 5d11cc9d7e0ee016d6b6c540d010b212291d61cd Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 25 Sep 2017 14:33:17 -0700 Subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO Add ACPI methods for gpio, scs and pcr. TEST=Boot to OS. Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/21685 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/acpi/pcr.asl | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 src/soc/intel/cannonlake/acpi/pcr.asl (limited to 'src/soc/intel/cannonlake/acpi/pcr.asl') diff --git a/src/soc/intel/cannonlake/acpi/pcr.asl b/src/soc/intel/cannonlake/acpi/pcr.asl new file mode 100644 index 0000000000..7915226a0a --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/pcr.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Method (PCRB, 1, NotSerialized) +{ + Return (Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} -- cgit v1.2.3