From 7f29896c773da31b31d3c4da7b8bfdfaacf691ad Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 3 Sep 2020 11:48:33 +0200 Subject: soc/intel/cannonlake: Add PCIe ports on PCH-H Fixes complains about missing INT configuration by the pciexp kernel modules. Tested with Linux 5.5 on Prodrive Hermes. Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/cannonlake/acpi/pcie.asl | 162 ++++++++++++++++++++++++++++++++- 1 file changed, 158 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/cannonlake/acpi/pcie.asl') diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 9c0933f92c..302863baba 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -54,7 +54,11 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 17, 21 +#endif + }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +66,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 18, 22 +#endif + }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +78,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 19, 23 +#endif + }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +90,11 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16 +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + , 20, 24 +#endif + }) { If (PICM) { Return (IQDA) } Else { @@ -367,3 +383,141 @@ Device (RP16) Return (IRQM (RPPN)) } } + +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} +#endif -- cgit v1.2.3