From 5ff742c740c3d39df85596a99046ef88aef5351f Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 27 Dec 2018 17:01:09 -0800 Subject: soc/intel/cannonlake: Add cannonlake ACPI GPIO op Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to implement GPIO toggling method, covered for both CNP_LP and CNP_H pch. BUG=N/A TEST=Build and boot up fine on sarien platform, add an dummy STSX in DSDT table, read back from iotools to confirm the GPIO tx state get updated. Signed-off-by: Lijian Zhao Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f Reviewed-on: https://review.coreboot.org/c/30461 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/acpi/gpio.asl | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) (limited to 'src/soc/intel/cannonlake/acpi/gpio.asl') diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index e05cb68642..1fa144f580 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,7 @@ #include #include #include - +#include "gpio_op.asl" Device (GPIO) { @@ -107,19 +107,3 @@ Method (GADD, 1, NotSerialized) Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 16))) } - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) - - Return (Local0) -} -- cgit v1.2.3