From 2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 17 Aug 2017 14:25:24 -0700 Subject: soc/intel/cannonlake: Add common ACPI support for CNL Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/acpi/globalnvs.asl | 57 +++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 src/soc/intel/cannonlake/acpi/globalnvs.asl (limited to 'src/soc/intel/cannonlake/acpi/globalnvs.asl') diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl new file mode 100644 index 0000000000..ac60b36d51 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/globalnvs.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Global Variables */ + +Name (\PICM, 0) // IOAPIC/8259 + +/* + * Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PCNT, 8, // 0x03 - Processor Count + PPCM, 8, // 0x04 - Max PPC State + TLVL, 8, // 0x05 - Throttle Level Limit + LIDS, 8, // 0x06 - LID State + PWRS, 8, // 0x07 - AC Power State + CBMC, 32, // 0x08 - 0x0b AC Power State + PM1I, 64, // 0x0c - 0x13 PM1 wake status bit + GPEI, 64, // 0x14 - 0x17 GPE wake status bit + DPTE, 8, // 0x1c - Enable DPTF + NHLA, 64, // 0x1d - 0x24 NHLT Address + NHLL, 32, // 0x25 - 0x28 NHLT Length + CID1, 16, // 0x29 - 0x2a Wifi Country Identifier + U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap + U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap + UIOR, 8, // 0x2f - UART debug controller init on S3 resume + + /* ChromeOS specific */ + Offset (0x100), + #include +} -- cgit v1.2.3