From 903c9764a16fba61bf90187d6f7e2afde37cfec0 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 20 Aug 2018 14:06:13 -0700 Subject: soc/intel/cannonlake: Change LPDDR4 to MEMCFG Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/Makefile.inc') diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 013e86a922..065d92b6e5 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -22,7 +22,7 @@ bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-$(CONFIG_UART_DEBUG) += uart.c -romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c +romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -- cgit v1.2.3