From 780a1c44e190427522ee27e887b2a9ab692eb594 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 22 Dec 2017 22:50:57 -0800 Subject: soc/intel/cannonlake: provide LPDDR4 memory init Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/22204 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/cannonlake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/Makefile.inc') diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 61318a4282..d4ca4072bd 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += memmap.c bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c +romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -- cgit v1.2.3