From 7673f2f5e9dab30c655d2d76d76394dd750459a6 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 5 Sep 2017 18:34:30 -0700 Subject: soc/intel/cannonlake: Add ramstage uart debug support Use fixed resources for LPSS uart devices for debugging purpose. BUG=NONE BRANCH=NONE TEST=Boot up with coreboot rom, without this changes, serial log will stop print anything during PCI resourcre setup as MMIO address of UART will be re-assigned. Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21412 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/Makefile.inc') diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 0490bf927b..0493c1b8ea 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -37,6 +37,7 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c ramstage-y += vr_config.c postcar-y += memmap.c -- cgit v1.2.3