From d5d89c8a55ee3a57fb30a7bca346076269266cab Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Tue, 7 May 2019 14:05:33 -0700
Subject: soc/intel/cannonlake: Fix pcie clock number

Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have
total 16 pcie clocks. It is different with pcie root port numbers.

BUG=CID 1381814
TEST=Build and boot up fine on sarien platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
---
 src/soc/intel/cannonlake/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/intel/cannonlake/Kconfig')

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c06b91eb48..e524275b8f 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -183,6 +183,11 @@ config MAX_ROOT_PORTS
 	default 24 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 16
 
+config MAX_PCIE_CLOCKS
+	int
+	default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+	default 6
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
-- 
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