From d37ebddfd84699464d076642f35fce0ef21cd1d5 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 30 Aug 2017 20:54:16 -0700 Subject: soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode. To maintian compatibilty with previous generation of SOC, select 32 bit mode as default. Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21296 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index df3cda1891..049b2bb0e5 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -60,7 +60,8 @@ config UART_DEBUG select CONSOLE_SERIAL select BOOTBLOCK_CONSOLE select DRIVERS_UART - select DRIVERS_UART_8250IO + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" -- cgit v1.2.3