From ce4c9ec4f61cfba8a25adf74ad40d582859ea8b8 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 14 Aug 2017 13:23:54 +0530 Subject: soc/intel/cannonlake: Add Kconfig option to select UART index Cannonlake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20998 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1b6759cd9b..fb2ed69794 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -56,6 +56,13 @@ config UART_DEBUG select DRIVERS_UART select DRIVERS_UART_8250IO +config UART_FOR_CONSOLE + int "Index for LPSS UART port to use for console" + default 2 if DRIVERS_UART_8250MEM + help + Index for LPSS UART port to use for console: + 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 + config DCACHE_RAM_BASE default 0xfef00000 -- cgit v1.2.3