From c8c741d9f9e4d9a91ef5b86a10ece56f8cf98a70 Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Tue, 29 Aug 2017 11:38:42 -0700 Subject: soc/intel/cannonlake: Define Max PCIE Root Ports This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati Reviewed-on: https://review.coreboot.org/21272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c32e4c2142..f72c2b302a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -92,6 +92,10 @@ config IED_REGION_SIZE hex default 0x400000 +config MAX_ROOT_PORTS + int + default 24 + config SMM_TSEG_SIZE hex default 0x800000 -- cgit v1.2.3