From b66757fc58b9bd025148d9db690009dec487fd0d Mon Sep 17 00:00:00 2001 From: Praveen hodagatta pranesh Date: Tue, 23 Oct 2018 02:43:05 +0800 Subject: soc/intel: Consolidate FSP CAR setup and teardown code This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - The new file apollolake/fspcar.c is addded to pass tempraminit parameters. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh Reviewed-on: https://review.coreboot.org/29209 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index abe029a194..161db33217 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO + select FSP_T_XIP if FSP_CAR config UART_DEBUG bool "Enable UART debug port." -- cgit v1.2.3