From a0368a0950bbd346b816c4397cfe9e86617d4f77 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Jun 2019 14:16:02 +0530 Subject: soc/intel/{cml, whl}: Add option to skip HECI disable in SMM This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 76906b2548..dac3522d0a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -107,6 +107,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR + select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE config DCACHE_RAM_BASE default 0xfef00000 -- cgit v1.2.3