From 8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 11 Jul 2017 12:33:22 -0700 Subject: soc/intel/cannonlake: Add postcar stage support Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fa5b8e4823..311cfb8a8c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -18,6 +18,8 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select INTEL_CAR_NEM_ENHANCED select PLATFORM_USES_FSP2_0 + select POSTCAR_CONSOLE + select POSTCAR_STAGE select REG_SCRIPT select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON @@ -76,4 +78,13 @@ config CPU_BCLK_MHZ int default 100 +# Clock divider parameters for 115200 baud rate +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + endif -- cgit v1.2.3