From 6539e10c4f209ea4273a78528b26c1f9ff4a3047 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 13 Sep 2018 11:48:43 -0400 Subject: drivers/intel/fsp2_0: Hook up IntelFSP repo With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Naresh Solanki Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 256cf1b6c7..cca783ff21 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -230,6 +230,10 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 +config CBFS_SIZE + hex + default 0x200000 + choice prompt "Cache-as-ram implementation" default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS @@ -257,4 +261,14 @@ config USE_CANNONLAKE_FSP_CAR endchoice +config FSP_HEADER_PATH + string + default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE + endif -- cgit v1.2.3