From 399c022a8c6cba7ad6d75fdf377a690395877611 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Tue, 11 Jul 2017 12:33:22 -0700
Subject: soc/intel/cannonlake: Add postcar stage support

Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/cannonlake/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/cannonlake/Kconfig')

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 1c0f1bffbe..483bb672b8 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -23,6 +23,8 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_INTEL_FIRMWARE
 	select INTEL_CAR_NEM_ENHANCED
 	select PLATFORM_USES_FSP2_0
+	select POSTCAR_CONSOLE
+	select POSTCAR_STAGE
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_BLOCK_SA
-- 
cgit v1.2.3